A low voltage, low power operational amplifier (op-amp) will be designed during this project. A 1.2 micron CMOS process will be used in the design. The op-amp will have a 1 volt peak to peak power supply and drive a 500 ohm resistive load with a power dissipation less than 20 milli-watts.

The design can be used for low voltage applications, such as battery powered electronics. The op-amp will be difficult to design due to the fact that the voltage supply is approximately the threshold voltage of a transistor.  The threshold voltage of the transistor limits the voltage swing in the input of an op-amp. Therefore, a new input stage will be especially designed to overcome this constraint for the input. The design needs to be able to drive a 500 ohm resistive load.  According to the equation,

in order to have a reasonable output voltage swing across the load resistance, the output stage of the op-amp needs to be able to drive approximately 1.5 milli-amp, which is difficult in a CMOS integrated circuit.  This design will be useful to the contemporary electronic industry, where the portability of products is important.

Edward K.F. Lee (Assistant Professor)

Iowa State University

Department of Electrical and Computer Engineering 2124 Coover Hall

Ames, Iowa 50011-3060

Voice: (515) 294-7686

FAX: (515) 294-8432

EMAIL: leekfe@iastate.edu

Team Members:

Chris Paone: Team Leader

Iowa State University

Major: Electrical Engineering

Address: 246 N. Hyland Ames, Iowa 50014

Voice: (515)296-2287

EMAIL: granor@iastate.edu

Alan Ngo

Iowa State University

Major: Electrical Engineering

Address: 212 North Franklin Ave. Ames, Iowa 50014

Voice: (515) 292-2554

EMAIL: pngo@iastate.edu

(Ray) Lui Lam

Iowa State University

Major: Electrical Engineering

Address: 111 Sheldon Ave Apt. #1 Ames, Iowa 50014

Voice: (515) 292-1637

FAX: (515) 292-1637

EMAIL: raylam@iastate.edu

Jason Gameon

Iowa State University

Major: Computer Engineering

Address: 4210 Lincoln Swing #14 Ames, Iowa 50014

Voice: (515) 296-1215

EMAIL: gmball@iastate.edu

The goal of this project is to implement, layout, document, and fabricate a low voltage low power op-amp, which can drive a 500 ohm resistor with a 1 volt power supply, using 1.2 micron CMOS technology by May 1999.  

In general, an op-amp can be divided up into three stages, the differential input stage, the gain stage, and the output stage as shown in Figure 1. The differential input compares the electric potential of input nodes and the gain stage amplifies the comparison result.  Finally, the output stage receives the signal from the gain stage and drives the output node.  Technical approach of each stage will be discussed below.

5.1 Differential Input Stage

Signal is fed into the op-amp through this differential amplifier.  A normal gate-input differential pair cannot be used because the threshold voltage drop limits the voltage swing.  In order to maintain the gain of the input, the PMOS and NMOS need to be in the saturation region.  The condition of the operation region is shown below.

For NMOS:

Therefore, a body-input differential amplifier is going to be used.

5.2 Gain Stage

Since the first stage is a body differential input pair, which has a very small gain, the second gain stage is needed. The common mode input range for the gain stage does not have to be big because the input is not rail-to-rail. The main requirement of the design for the gain stage is that the gain has to be huge. A typical gain stage is a common source amplifier. This gain stage has a gain ranged from 30 to 60 volt/volt, which is not enough. Therefore, a cascode configuration will be used. This is a comparison between the gain of common-source amplifying stage and a cascode amplifying stage with an assumption of all transistors are operating in saturation region.

(While g_m is the trans-conductance of a MOSFET operating in saturation region and r_DS is the output impedance of a MOSFET operating in saturation region)

Using the cascode configuration, the gain of the second stage can be increased up to 1000 to 3000 volt/volt. However, to guarantee all the transistors are operating in the saturation region, V_DS of every transistor has to be greater than its V_eff, which is generally defined as V_GS – V_T. Therefore, the minimum output voltage of a common-source amplifying stage is V_eff, when that of the cascode amplifying stage is 2 V_eff. V_eff can be ranged from 0.1 to 0.4 volt. As a result, the output swing of the second stage will be very limited. Moreover, since the V_eff must be small to maintain a reasonable output swing, V_GS must be slightly greater than V_T. This makes the biasing of circuit very hard. Understanding, the problem, we selected cascode amplifying stage. This is because that the gain is more important than biasing and the output swing. Although biasing is hard, there are some tricks to guarantee all the transistors operating in saturation. Employing an output stage, the output swing problem can be solved. Finally, since the output range of the first stage is not known, the detail design of the gain stage will be left over to next semester.

5.3 Output Stage

The output stage is used to solve output swing and small output current problem. Since the bias current of the gain stage is small, it is not sufficient to drive the low impedance load. The following calculation shows the amount of current the output stage must be able to drive in order to have rail-to-rail output voltage swing.

R_Load = 500 ohms

V_{out max} = 0.5 volt

Therefore, the output stage must be able to drive at least 0.5/500 = 1 milli-ampere.

In order to drive this big current, the transistors size must be huge, because a large effective voltage limits the output voltage swing. From the I-V characteristic equation of saturated MOSFET,

Since the effective voltage is less than 1 volt, we have to increase the width-length ratio a lot, in order to get a small effective voltage drop.

Another issue about the output stage is that the DC current must be small for minimum power dissipation. Therefore a class AB output stage will be used. The characteristic of a class AB output stage can be shown from the following graph.

As shown in the graph, class AB keeps the current flow between power supplies low. The only time the DC current from V_DD to V_SS is large is during the low-to-high or high-to-low transactions. In this way, the power dissipation is minimized. If the output swing is not large enough, feed-backward or feed-forward bias control may be included.

The body input stage show in figure 7 was simulated using Cadence’s Analog Artist. The first simulations completed used a level 3-transistor model. These simulations were used to determine all of the node voltages. Hand calculations were used to determine the most likely range of currents that would result in node voltages under one volt. Simulations were run using the values in table 1 seen below.

Unfortunately, all of the simulations had at least one node voltage that was above one volt. The differential pair was then redesigned. The transistor "T2" shown in figure 7 was eliminated because the node above it was always outside of the voltage requirements.

The schematic was then redesigned resulting in figure 3 (page 3). The body effect used by the differential pair is not modeled very accurately in a level 3 model. To increase the accuracy of the simulations the transistor model was changed to Mosis’ N86N level 49 model found at http://www.mosis.com/. After the model was changed several simulations were run on the new schematic. With the new model it was discovered that the parasitic diode created from the source of the PMOS transistor to the substrate was not sufficiently biased. This resulted in a tremendous current loss into the substrate at common mode range below 0.2 volts. Several different biasing currents and voltages were used to attempt to remedy this problem. However, the voltage that needed to be lowered was also proportional to the output current. It would be impossible to drive a 500 ohm resistive load with the current required to keep the diode off at all times. The design team is now looking into a way to use both the classic differential pair design and the new body input design. The schematic shown in figure 8 shows a conceptual design. A classic differential pair will be used for all voltages below a common mode range of 0.2 volts, after this common mode voltage is exceeded the body input differential pair will be used. The design team has had several difficulties with this design, but are currently pursuing solutions.

The following table is the proposed budget for the two semesters: