16-Bit Digital Accumulator May99-00 Senior Design Project

Contents of this Page

Abstract
Problem Statement, Background or Context for the project
Design Objectives
Technical solution to problem and/or technical achievement of design objectives
Recommendations for continued and/or additional work on either the specific or the general project problem.
Human Effort Expended
Total Cost
Final Gantt Chart
Lessons Learned
Other

SLIDES SHOW

ABSTRACT

This project is to design, simulate and document a 16-bit digital accumulator (16BDA).

The 16-bit digital accumulator (16BDA) will operate at low power supply and high clock frequency between 600MHz and 1GHz with minimum power consumption using 0.35mm CMOS technology to design.

The 16BDA will be use in Direct Digital Synthesizer (DDS) by our client, Professor K.F. Lee. The 16BDA is composed of multiple 1-bit adder and Flip-Flop register modules. The application of 16BDA to DDS enables high bandwidth output frequency tuning resolutions. The 16BDA is the most critical part concerning the speed of DDS throughput, thus we will need to design the 16BDA with the fastest possible speed.

This report describes the updated 16BDA design strategies with problem statement, design objective, technical approach, design simulations, budget chart, and proposed schedule in Gantt Chart format. On top of that, an appendix or glossary of technical terms is also included at the back of this report.

PROBLEM STATEMENT

An accumulator consists of adders and data storage registers e.g. Flip-Flop (FF) (See Appendix). Typical accumulator operates at the speed of 10-30MHz and this speed limitation is due to the propagation delay of the adders.

Since we will use this 16BDA in DDS at the operating frequency between 600MHz & 1GHz and one of the slowest parts of DDS is the adder in digital accumulator, we need to design a faster respond adder.

The operational speed of FF determines the correctness and accuracy of the functionality of 16BDA. To ensure the 16BDA is error-free, FF in the 16BDA is able to operate at the clock frequency rate or higher. This ensures that FF can correctly capture and store every incoming data.

BACKGROUND
Our project advisor and client, Professor Edward Lee K.F. is in the progress of designing a Direct Digital Synthesizer - DDS (See Appendix) which provide many advantages over different approach in generating a high-speed signal.

DDS uses a direct method for generating the required signal and is different from the more familiar indirect method phase-locked-loop (PLL) systems.

In a DDS, a representation of the waveform is built up digitally, and then it is converted into an analogue format for use by circuitry in the conventional manner. To generate a waveform in this manner, four basic circuit blocks are required as shown in following figure. There is a digital phase accumulator, a waveform map, a digital to analogue converter and finally a filter.

In our project, we are concentrating in designing the digital accumulator block at high frequency respond time in an optimal area so to couple the digital accumulator into the DDS.
 
 

3. DESIGN OBJECTIVE

The goal of this project is to design, simulate and document a 16-bit digital accumulator (16BDA). The 16BDA will operate at 3.3V, low power supply at high clock frequency between 600MHz and 1GHz using 0.35mm CMOS technology in compact size. The power consumption of the 16BDA is keep to minimum and should be less than 100mW.

DESIGN SPECIFICATIONS

The 16BDA will be design using 0.35mm CMOS technology and operate under the following conditions:

• Operating clock frequency range between 600MHz and 1GHz
• Supply voltage of 3.3V

Power consumption less than 100mW

6. TECHNICAL APPROACH

6.1 Hardware Design

The 16BDA is composed of 1-bit register and 1-bit adder. The operational speed of adder is the main concern to the time constrains. In practice, ordinary phase accumulator (See Appendix) circuits cannot complete a 16-bit addition in a short clock period because of the delay caused by the carry bits propagation through the adder. In order to enhance the operation of 16BDA to higher clock frequencies, one solution is pipelined accumulator (See Appendix).

Another approach to enhance the operation of 16BDA to higher clock frequencies is to shorten the operational time in 16BDA. Dynamic logic (See Appendix) and True Single-Phase Clocking Latch (TSPC) (See Appendix) help speeding up the operational speed in logic gates by improving the sensitivity to the clock triggering. In addition, the design consists of large number of FF. In other words, FF dominantly determines the operational speed. We apply Dynamic logic and TSPC to implement a fast respond FF. For some cases, circuit simplification can help to shorten the operational time. In the project of 16BDA, circuit simplification does not help on improving the system speed because the circuit is already very direct, clear and simple. One of the ways to shorten the operational time is to fasten every single component by dynamic logic technique. Again, Dynamic logic and TSPC latch are applied in register and adder to optimize the operational speed. Besides, they also help on getting a better power consumption.

6.2 Circuit Simulation

Circuit simulation is crucial in this project. Maturely developed design automation software – Cadence (See Appendix) is introduced to accelerate and advance the design process of 16BDA. Design automation software simplifies and optimizes the circuit simulations for the 16BDA-functionality verification.

6.3 Layout Realization

Once the logical scheme of the 16BDA is decided, the layout design approach for the 16BDA is transistor-by-transistor because library cells (single gates or function blocks) are meant for low clock frequencies but not for the high clock frequency range of 600MHz to 1GHz. The layouts for the adder and other basic logic blocks in the 16BDA have to be custom-made. Moreover, customized cells give a better area optimization.

TECHNICAL SOLUTION

As mentioned in the technical approach, we will use pipeline architecture, dynamic logic and TSPC latch in our 16BDA-circuit design.

Dynamic Logic

Dynamic logic is chosen to use in this circuit because it has a low direct current power dissipation and operational speed is enhanced. However, there are some problems for using the dynamic logic. There is charge redistribution (charge sharing) which leads to the losing of the output voltage. In addition, leakage of current due to charge redistribution leads to the variation of the power supply.

In order to overcome the problem of charge redistribution, an inverter is added to the output of the dynamic logic circuit called a domino dynamic logic. A domino dynamic logic does not only provide low direct current power dissipation and high operational speed; it does not have the problem of charge redistribution.

Pipeline Architecture

Pipeline architecture (Diagram See Appendix) is used because there is only one clock cycle delay for a set of data, in our case; the data is a 16 bit binary number, to be outputted. In addition, the next set of the data can be obtained after one clock cycle. Therefore, pipeline architecture can minimize the speed of a series of data outputted.

However, there is a disadvantage of using pipeline architecture. Latency, the time it takes from when operands are introduced to the data processing element to when outputs are available from the module, is long. In the 16BDA, it has a latency of sixteen clock cycles. Fortunately, the latency is not important in our design.
 

PROGRESS REPORT

In this semester, we had designed the architecture of an adder and a DFF. In this section, we are going to discuss our designs a little bit in details.

FF

A FF is a storage device, which holds some data within a clock period. There are some points that we need to consider when we designed the FF. We had to pay attention to the clock distribution in order to minimize the clock skew, the fault output signal of the clock. Also it is necessary to ensure that the clock speed is above 40MHz in order to minimize the signal lost. We should equalize the rise time and fall time of the FF in order to archive the minimum time delay of the output signal. Moreover, we need to minimize the size of the FF in order to avoid the high output load introduced to one of the latch, which induced the time delay.

A FF always included a latch as a signal storage module. In our design, we chose using TSPC latch. It was chosen because of its low power consumption and small size, which can reduce the chip area. In additions, it is the simplest clocking method, which is easily applied to a circuit. A dynamic logic is applied to this clocking method to optimize the speed and density at the expense of circuit that is more detailed and system. Here below we show the block diagram of a dynamic TSPC latch.

Adder

As mentioned before, an adder is a very important design because it is the module which affects the speed of the accumulator. In our accumulator, we will use a single-bit adder to do the accumulation because it is the most generally and commonly used adder which is easily to be understood. Moreover, it has a small size. Right now, we are still designing the architecture of the design.

An implementation of an adder is shown below:

  SUM = ABC + AB’C’ + A’B’C + A’BC’

= C (AB + A’B’) + C’(AB’+A’B)

= A Å B Å C

CARRY = AB + AC + BC

 Where A and B are the adder inputs, C is the carry input, SUM is the sum output, and CARRY is the carry output.

 What we had considered is that we will use the single-bit adder to be the circuit to do the addition, and then we will improve our circuit by applying the dynamic logic.
 
 
 

Task	Description	Date	Members Involved	Finsihed on Time
Logic Gate Level Design	Inverter/Buffer  To design, simulate and layout an inverter which will be applied to other logic block. Two inverters are connected in series to form a buffer.	Jan 8, 99 – Jan 18, 99	Wing-Yee CHU  Wai-Ming Yung	YES
Block Level Design	FF Use the inverter and NAND gate to design and simulate a FF. Different designs are built and tested, the one has the highest operational speed will be chosen for later use. At last layout the chosen design of the FF.	Jan 18, 99 – Feb 16, 99	Voon-Yew CHEE  Wing-Yee CHU	YES
	Adder Use the inverter and NAND gate to design and simulate an adder. Different designs are built and tested, the one has the highest operational speed will be chosen for later use. At last layout the chosen design of the adder.	Feb 17, 99 – Mar 5, 99	Wing-Yee CHU  Wai-Ming YUNG	YES
	1-bit, 4-bit, 8-bit Accumulator Blocks Put adders and DFF together to design and simulate the basic module of 1-bit, 4-bit, 8-bit.	Mar 5, 99 - Apr 20, 99	Wing-Yee CHU	YES
Circuit Integration	16BDA Put the 1-bit, 4-bit and 8-bit together to design, simulate and layout a 16BDA.	Apr 20, 99 - Apr 26,99	Wai-Ming YUNG  Voon-Yew CHEE  Wing-Yee CHU	YES
Project Finalization	Final Report To write a final with a detailed description of each component and the usage them. The final layout and the specification of the 16BDA are included in the report.	Apr 1, 99 – May 10, 99	Wai-Ming YUNG  Voon-Yew CHEE  Wing-Yee CHU	YES
	Oral Presentation To have a formal presentation to the public in order to explain the detailed of our project.	To be informed	Wai-Ming YUNG  Voon-Yew CHEE  Wing-Yee CHU	YES
On-going Task	Web page updated To continue update the Gantt chart of the team homepage	Jan 8, 99 – May 10, 99	Wai-Ming YUNG  Voon-Yew CHEE  Wing-Yee CHU	YES

 

16BDA Design Flow

Design Entry
The first step of 16BDA Layout Design is Design Entry. The purpose of design entry is to describe the designed circuit of 16BDA to a set of electronic-design automation (EDA) tools – Cadence package.  Basically, the design entry of 16BDA is categorized in Hardware Design Language Entry, Schematic Entry and Layout Entry.
Hardware Description Language (HDL) Entry
HDL is to describe the circuit of 16BDA to a set of EDA in text manner for functionality test.  As the circuit of 16BDA is a clean and simple circuit and also because of the time-efficiency, HDL Design Entry was skipped and were going straight to Schematic Design Entry instead.  The following is an example of written an adder in VHDL format.

A full adder in VHDL
entity Full_Adder is
generic (TS : TIME := 0.11 ns; TC : TIME := 0.1 ns);
port (X, Y, Cin: in BIT; Cout, Sum: out  BIT);
end Full_Adder;
architecture Behave of Full_Adder is
begin
Sum  <= X xor Y xor Cin after TS;
Cout <= (X and Y) or (X and Cin) or (Y and Cin) after TC;
end;

VDHL is used for the documentation, simulation and verification for microelectronic circuit.  EDA will understand VDHL and provide an environment for circuit simulation and verification.  Again, because of the maturity of 16BDA circuit and time-efficiency, the HDL Entry is skipped and Schematic entry was the first step in the project.
In fact, the HDL - Verilog was recommended to be used under Cadence environment and the Verilog compiler - Verilog-XL came with the Cadence package.  In addition, Iown State University was emphasis on Verilog in most VLSI courses.

Schematic Entry
As mentioned above, HDL entry was skipped and Schematic Entry was the first step of Layout Design in the project of16BDA.  Schematic Entry is the most common method of design entry for microelectronic circuit and is likely to be useful in one form or another for some time.  The commonality of Schematic Entry and the accessibility of Schematic Entry provided by Cadence were the reasons for using Schematic Entry in 16BDA.  In fact, HDL Entry is replacing the conventional (Low-Level Entry) gate-level schematic entry, but new graphical tools (like Cadence) based on schematic entry are now being used to create large amounts of HDL code.

Circuit schematics were drawn on Cadence under the tools named Schematic Composer.  The provided basic cells under Cadence environment were P-MOS and N-MOS.  The commonly recognized electronic symbols of P-MOS and N-MOS were used by Cadence as the P-MOS and N-MOS circuit symbol in Schematic Entry.  The symbols contain connections for Gate, Source, Drain and Substrate.  Transistor Sizing was done in this level.  The size of the transistor (P-MOS or N-MOS) can be customized, initialized, and parameterized thought the (pop-up) Transistor File Table by double-clicking the correspondent transistor symbol in the circuit.  Inter-wiring between transistors was also done in this level by drawing a line between connection points or transistor pins.  Apart from Transistor symbols, Power and Signal sources were necessary to be included in the schematics.  Again, every single source had a Source File Table similar to Transistor File Table. The Source File Table allowed you to set the timing, initial voltage and all necessary settings for the source.  In 16BDA, the testing clock frequency was 1GHz.  The time period is 1ns.  Therefore, the highest frequency had to be 1GHz or lightly higher than 1GHz so as to ensure the 16BDA’s correct functionality.

Hierarchical Design
Hierarchical Design was important to 16BDA Layout Design because Hierarchy reduced the size, simplified the complexity of 16BDA.  With respect to leaf cells, 16BDA needed only 2 leaf cells – DFF and ADDER.  As a matter of fact, 16BDA consisted only  2 level of hierarchies because of the simple complexity of the circuit.

The Cell Library
In 16BDA, because of the operating speed constraint, the Cell Library was not applicable to the project.  The second reason was that 16BDA applied the Dynamic Logic technique that was different to the technique applied to the ordinary provided cells in the library.  To explain in another way, the cells provided in the Cadence Library were not CLOCKED elements. So, the Cell Library that was provided under Cadence environment was not applicable to 16BDA.  We built our own Cell Library with clocked DFF and ADDER.

Logic Synthesis
Logic Synthesis is to provide a link between a HDL and a netlist.  As mentioned above, HDL was not used and graphical entry (Schematic Entry) was used instead.  In 16BDA, Logic Synthesis was not involved.

SIMULATION
Type of Simulation
The following are the ordinary simulation modes:
. Behavioral Simulation
. Functional Simulation
. Static Timing Analysis
. Gate Level Simulation
. Switch-Level Simulation
. Transistor-Level or Circuit-Level Simulation

In 16BDA, again because of the maturity of circuit design and only schematic entry was used, the following were the simulation modes that were involved in the 16BDA project.
. Static Timing Analysis
. Gate Level Simulation
. Switch-Level Simulation
. Transistor-Level or Circuit-Level Simulation

Static Timing Analysis
Static Timing Analysis is to verify the longest time delay in the 16BDA circuit.  In other words, we were finding the longest or critical path delay in the circuit under the worst-case operating conditions: Vdd = 3.3V, and T = 100 degree.  The timing analyzer gave us only the critical path and its delay.  The timing analyzer was not giving us the input vector that would activate the critical path.  In 16BDA, the critical path was determined by the internal paths in the ADDER because the timing delay of ADDER was input-sensitive. The DFF had no critical path as it had only one path.
 

Gate-Level Simulation
As mentioned, the timing analyzer could only offer us the guarantee that there was no other path that was slower than the critical path.  When came down to the Gate-Level, we started by trying to find input vectors that activate the critical path by working forward from the beginning of the critical path.  In our project, because of the circuit simple complexity, we were able to test the ADDER by inputting all possible input combinations.  This allowed us to have an accurate Gate-Level Simulation without going thought complicated Input, Output and Net capacitance calculations.

Net Capacitance
As mentioned above, because of the simple circuit complexity, net capacitance estimation was quite simple by providing all possible input combinations to the circuit and measuring the critical path delay.  Simultaneously, the simulation was adding capacitance to the outputs of each of the logic cells to model the parasitic net capacitance that would be present in the physical layout.  The simulation added 0.01pF on each node and another 0.01 pF for each pin (logic cell input) attached to a node.  This simulation allowed predicting the wire-load, wire-delay and interconnect model.

Logic Systems Simulation
16BDA were purely a digital system/circuit.  As a matter of fact, Digital signals are actually analogue voltage (or current) levels that vary continuously as they change.  Digital simulation that digital signals may only take on a set of logic values from a logic system.  But, in 16BDA, because of the more accuracy of time analysis against digital system, analog signals testing was used instead of two-value (0 or 1) logic system simulation.  By putting 16BDA into an analog simulation environment, we was able to get more accurate propagation, rise/fall time, signal-resolution and resistive strength analysis.  At the same time, we were also able to have more accurate pin-to-pin, pin and net/wire delay figures.

Switch-Level Simulation
Switch-Level Simulation is a more detailed level of simulation than we have mentioned above. The figure below shows the circuit schematic of a true single-phase flip-flop using true single-phase clocking (TSPC). TSPC has been used in 16BDA to attempt to save area and power.
(a)

(b)

A TSPC (true single-phase clock) flip-flop.  (a) The schematic (all devices are W/L = 3/2) created using a Compass schematic-entry tool. (b) The switch-level simulation results. The parameter charge Decay Time sets the time after which the simulator sets an undriven node to an invalid logic level (shown shaded).

In a CMOS logic cell every node is driven to a strong '1' or a strong '0'. This is not true in TSPC, some nodes are left floating, so we ask the switch-level simulator to model charge leakage or charge decay (normally we need not worry about this low-level device issue). The result diagram shows the waveform results. After five clock cycles, or 100ns, we set the charge decay time to 5ns. We notice two things. First, some of the node waveforms have values that are between logic '0' and '1'. Second, there are shaded areas on some node waveforms that represent the fact that, during the period of time marked, the logic value of the node is unknown. We can see that initially, before t = 100ns (while we neglect the effects of charge decay), the circuit functions as a flip-flop. After t = 100ns (when we begin including the effects of charge decay), the simulator tells us that this circuit may not function correctly. It is unlikely that all the charge would leak from a node in 5 ns, but we could not stop the clock in a design that uses a TSPC flip-flop. In ASIC design we do not use dangerous techniques such as TSPC and therefore do not normally need to use switch-level simulation.

A switch-level simulator keeps track of voltage levels as well as logic levels, and it may do this in several ways. The simulator may use a large possible set of discrete values or the value of a node may be allowed to vary continuously.

Transistor-Level Simulation
In 16BDA, we also needed to simulate a logic circuit with more accuracy than provided by switch-level simulation. In this case we turn to simulators that can solve circuit equations exactly, given models for the nonlinear transistors, and predict the analog behavior of the node voltages and currents in continuous time. This type of transistor-level simulation or circuit-level simulation is costly in computer time. It took 3 hours at least to simulate 16BDA using the circuit-level simulator provided by Cadence - SPICE. We were using SPICE and providing the P-MOS and N-MOS model 49 for SPICE’s internal calculation under Cadence environment.
 
 
 

TESTING
In 16BDA, again because of the maturity and the simple complexity of the circuit, the following were the tests that were involved in the 16BDA project.
. Functionality Test
. Unit Test
. Module Test
. System Integration Test
. System, Interfacing, I/O Test
Those mentioned tests would be focused on integration, functionality, signal level, rise/fall time, delay and power prospective.

Functionality Test
The main goal was to test the functionality of the 16BDA and to make sure the circuit design meets with the requirements and specifications.  To ensure the correctness of the functionality of 16BDA, the best way was to provide all possible combination to the system and matched the output pattern with the predicted output pattern.  The problem of testing all possible combinations was time.  Testing all possible combination was not time-effective enough.  The testing technique of test range partitioning was inducted.  We partitioned all possible input into ranges and only the minimum and the maximum value of a range would be tested. By selectively selecting some of the representative input test patterns, number of test value decreased down to the time-affordable and time-effective level.  Functionality test was the first test to be done before going on further test.

Unit Test
Unit test was to divide the entire system into tiny unit that allowed us to carry out simple test on that unit.  After making sure the correctness of an unit, we could go on to another units.  This test technique was considered as divide-and-conquer.  This test scheme allowed us to test all the leaf cells one by one, piece by piece.  After ensuring the proper functionality of every single unit, we could move to module test.

Module Test
Similar to unit test, module test was just in a larger dimension.  Module was a collection of units. After doing the unit test, the next step is module test because all the leaf cells had been tested.  The problem was that although all leaf cells were working properly, there was a chance that the module was not working as what we predicted because of  unit interfacing, charge sharing or other technical issues.  After module test, we should have a conclusion that whether all modules were working properly or not.  If one of the module was not working, we might need to straight from unit test all over again until the module was fixed and was working properly.

System Integration Test
System Integration Test was the same as module test, again, in a greater dimension.  A System is a collection of modules.  By applying the same concept of Module test to Unit Test, System Integration Test was to test the proper integration of modules.  If one of the module was not working properly, we might need to go back to unit test and module test so as to clarify and to spot out the problem.  After locating the problem source, we would be able to fix the problem.
 

System, Interfacing, I/O Test
System, Interfacing, I/O Test was to integrate the system with I/O and all interface units.  The goal was to test the successfulness of system interfacing.  Issues like power, current, and voltage level sufficiency for system interfacing would be tested.  For example, there is a possibility that the system is working properly but providing a very weak output that is not sufficient enough for the perception of the output buffer.
 

Physical Design
In 16BDA, physical design was divided intro system partitioning, floor planning, placement and routing.

System Partitioning
16BDA only consist 2 leaf cells – DFF and ADDER.  As a matter of fact, system partitioning is not necessary in 16BDA.  Somehow, system partitioning helps on the system simulation. In 16BDA, we were able to locate the most complicated combination in terms of interfacing.
 
 

The above was a partition used for system simulation.  The above partition is considered as the most complicated partition in the system in terms of interfacing since the other parts of the system were just a combination of the above partition adding on more DFF.
 

Floorplanning
One of the objective for floorplanning is to predict the interconnect delay by estimating interconnect length. The input to a floorplanning tool is a hiearchical netlist that describes the interconnection of the blocks like buffer, inverter, DFF, ADDER.  The netlist is a logical description of 16BDA.  Floorplanning is thus a mapping between the logical description (the netlist) and the physical description (the floorplan).
The goals of the floorplanning are to:
. arrange the blocks on a chip,
  In 16BDA, the horizontal to vertical ratio was trying to be 1:1
. decide the location of the I./O pads
  In 16BDA, I/O is not involved
. decide the location and number of the power pads
  In 16BDA, power pads are not involved
. decide the type of power distribution and,
  In 16BDA, the power distribution was quite even because of the simple complexity
  of  16BDA
. decide the location and type of clock distribution,
  In 16BDA, clock was planning to be passed in horizontal manner

Throughout the 16BDA, we needed to predict the performance of the final layout.  In floorplanning we wish to predict the interconnect delay before we complete any routing.  To predict delay we need to know the parasitic associated with interconnect: the interconnect capacitance (wiring capacitance or routing capacitance) as well as the interconnect resistance.  At the floorplanning stage, we knew only the fanout of a net and the size of the block that the net belonged to.  We could not predict the resistance of the various pieces of the interconnect path since we did not yet know the shape of the interconnect for a net.  However, we could estimate the total length of the interconnect and thus estimated the total capacitance.  We estimated interconnect length by collecting statistics from previously routed chips and analyzing the results.  From these statistics we created estimation that predict the interconnect capacitance as a function of net fanout and block size.  A floorplanning tool can then use these predicted-capacitance estimation.

I/O and Power Planning
16BDA is the first block in DDS and will be connecting a lookup table (ROM) that is the second block of DDS.  Signals flow onto and off the 16BDA block and we needed to supply power.  We needed to consider the I/O and Power constraints early in the floorplanning process.  16BDA will be a part of the DDS chip.  The silicon chip is mounted on a chip carrier inside a chip package.  Connections are made by bonding the chip pads to fingers on a metal lead frame that is part of the package.  The metal lead-frame fingers connect tot the package pins.  The chip or die will consist of a logic core inside a pad ring.  On a pad-limited chip or die we may use the tall, thin pad-limited pads, which maximize the number of pads we can fit around the outside of the chip.  Special power pads are used for the positive supply ,or VDD, power buses (or power rails) and the ground or negative supply, VSS or GND.  Usually, one set of the power to the I/O pads only.  Another set of VDD/VSS pads connects to a second power ring that supplies the logic core.  Lastly, I/O pads also contain special circuits to protect against electronstatic discharge (ESD).  These circuit can withstand very short high voltage (several KV) pulses that can be generated during human or machine handling.
 
 
 
 

Human Effort Expended

This project took about 210 working hours/per team member for 2 semesters and the total effort expended hours was 637 working hours for 2 semesters.
 

Total Cost

This project spent $55 for poster and $7.5 for secretarial expenses.  All other resources ( like Cadence VLSI Design Package ) were provided by Iowa State University.
 

Human Effort Expended and Total Cost table
 
 

Phase	Project Task	Effort Hours		Budget
		Proposed	Actual	Proposed	Actual
1	Introduction to team and advisor	1	1	$0	$0
	Analyst the problem statement of the project	2	3	$0	$0
	Research on internet and library	50	72	$5	$2
	Project Plan	30	46	$5	$5.5
	Project Poster	50	69	$70	$55
	Design Review	30	38	$5	$0
	Setup and research total	163	229	$80	$62.5
2	Design, simulate and layout an inverter/buffer	40	9	$0	$0
	Design, simulate and layout an adder	40	13	$0	$0
	Design, simulate and layout a DFF	40	19	$0	$0
	Subsystem design phase total	120 hrs	41 hrs	$0	$0
3	Design a 16BDA	50	0	$0	$0
	Simulate the 16BDA	30	0	$0	$0
	Review of the final circuit design	40	0	$0	$0
	Oral presentation	40	0	$5	$0
	Final Report	50	0	$5	$0
	Testing and prototype phase total	210 hrs	0 hr	$10	$0
Misc.	Class meeting	96	48	$0	$0
	Team meeting	48	42	$0	$0
	Miscellaneous total	144	90	$0	$0
	OVERALL TOTAL	637 hrs	360 hrs	$90.00	$62.50

FINAL GANTT CHART

Lessons Learned

. Communication skill
. Problem solving skill
. Design methodology
. Project management
. Time management
. VLSI Circuit Design Methodology
. Secretarial skill

CONCLUSIONS

In this project, we faced quite a difficulty searching for the best design in our project. There is a lot of information about digital accumulators in the research papers or on the web, and we had to choose the design which is best fits to our project. We will complete all of the tasks shown on the Gantt chart with the exception of a completed working prototype. At the time this document was developed, we are still designing the project. We hope that we will complete this project before the final presentation. The end project of this project will be a carefully simulated design layout.  No installation will be needed.

By the way, in this project, we learnt a lot in communication with the team members and the advisor. In additions, we learnt to write technical documents to present our project. Finally, we are all appreciated that we can work on a digital accumulator project.

PROJECT CLIENT AND ADVISOR

Professor Edward LEE

Address:

TEAM MEMBERS

Wai-Ming YUNG remyyung@iastate.edu

Voon-Yew CHEE vychee71@iastate.edu

Wing-Yee CHU friendly@iastate.edu

APPENDIX

DDS

DDS has been recognized as technology for generating highly accurate and frequency-agile (rapidly changeable frequency over a wide range), low-distortion output waveforms. DDS architecture (Figure 1) employs a precision pipelined 16BDA and digital signal-processing techniques to generate a digital sine wave representation, which is referenced to a highly stable reference clock. The digital sine-wave data is then applied to a high-speed D/A converter (DAC) to generate a corresponding analog sine wave output signal.

Phase

A complete cycle corresponds to one complete revolution. Points on the waveform can be related to a point on the circle and expressed as a given angle. The picture of a point moving around a circle is a very convenient visual aids because the position on the circle at any given time corresponds to the phase. Any increase in the position around the circle corresponds to an advance in the phase.
 
 

Phase Accumulator

A phase accumulator is an adder followed by a register. It adds repeatedly the same input value, which is called Frequency Setting Word (FSW). The looping accumulation enables the output to repeatedly reach the maximum value or overflow. When overflow occurs, the overflow bit is cut off and the output value will be all '0'. In other words, a new cycle continues the addition. In 16BDA, this means that if the output is higher than 65535 (in decimal) or 1111 1111 1111 1111 (in binary), the output value will be '0' (i.e. 1111 1111 1111 1111 + any FSW = 0000 0000 0000 0000 with overflow). In this case, the FSW controls the frequency as well as the time period of the generated output staircase waveform. The higher value of FSW, the shorter the period and the higher the frequency of the output waveform.
 
 

TSPC Latch

TSPC latch is the simplest clocking methodology, which uses a single clock in conjunction with the register.
 
 

Pipeline Architecture

Pipeline is to divide a big stage in smaller independent combinatorial sub-stages (or sub-tasks), that works at the same time on a part of the throughput. In every sub-stage, a register stores the result of the previous sub-stage and feeds it to the following stage at the following clock pulse.
 
 

Dynamic Logic

Domino Dynamic Logic

Domino logic gate is shown in the above. During the precharge phase, Z is disconnected from ground, since transistor MN is off. PMOS transistor MP is on during precharge and node Z is charged to VDD. Therefore, the output Vout is always zeros during the precharge phase. During the evaluation phase, MP turns off and MN turns on; node Z will either discharge to 0 if both A and B are high, or stay at VDD otherwise. If Z is discharged, Vout will rise to VDD; otherwise, it will stay at zero.
 
 

CADENCE

CADENCE is the design automation software that accelerates and advances the process of designing electronic systems. It can be used to draw a schematic of a circuit design, do the simulation, draw the layout, and verify the mismatching between the schematic and the layout.
 

REFERENCES
 

    1.   Cheng, "Dynamic Logic Circuit"

http://ug.ee.tku.edu.tw/~vlsi/cheng/ch5/5-2/5-2.htm

http://cas.et.tudelft.nl/~wissce/reports/giaco/main_html.html

http://www.analog.com/publications/magazines/Dialogue/30-3/single_chip.html

http://cas.et.tudelft.nl/~wissce/reports/giaco/main_html.html

http://cas.et.tudelft.nl/~aardoom/gps93/gps93.html

    7.   Charles G. Ekroot, Member IEEE, and Stephen I. Long, Senior Member, IEEE, "A GaAs 4-bit Adder-Accumulator Circuit for Direct Digital Synthesis", in 1988, IEEE Journal of Solid State Circuits, Vol 23, No. 2, April 1988. Pp. 573-579.

    8.   Jouko Vankka, Student Member, IEEE Mikko Waltari, Student member, IEEE, Marko Kosunen, and Kari A. I. Halonen, "A Direct Digital Synthesis with an On-Chip D/A Converter", in 1998, IEEE Journal of Solid State Circuits, Vol 33, No. 2, February 1998. Pp. 218-227.

    9.   Neil H.E. Weste, Kamiran Eshraghian, "Principles of CMOS VLSI Design" ISBN 0-201-53376-6, Addison-Wesley Publishing Company, 1994.
 
 

© Copyright Iowa State University 1998